1. Field of the Invention
The present invention relates to a semiconductor device and fabricating method thereof, and more particularly, to a semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a fabricating method thereof.
2. Discussion of the Related Art
FIGS. 1 and 2 illustrate a related art semiconductor device having a high-voltage transistor and a PIP capacitor.
Referring to FIG. 1, a well region (not shown) and an n− extended drain region 110 are formed in a high-voltage transistor area of a p− substrate 100 having a high-voltage transistor area and a PIP capacitor area. Subsequently, a LOCOS device isolation layer 120 is formed as a device isolation layer. After a pad oxide layer (not shown) for forming the LOCOS device isolation layer 120 has been removed, an oxide layer 130 to be used as a gate insulating layer in the high-voltage transistor area is formed over the substrate. A polysilicon layer 140 and an insulating layer pattern 150, e.g., an oxide layer pattern, are formed on the oxide layer 130 and the LOCOS device isolation layer 120. The insulating layer pattern 150 covers the entire high-voltage transistor area but exposes a surface of the polysilicon layer 140 corresponding to a PIP capacitor forming area within the PIP capacitor area. Subsequently, the exposed surface of the polysilicon layer 130 in the PIP capacitor area is doped with phosphorus oxychloride (POCl3).
Referring to FIG. 2, the insulating layer pattern 150 is removed. By patterning the polysilicon layer 140 in the high-voltage transistor area and the PIP capacitor area, a gate conductive layer pattern 141 and a first electrode layer pattern 142 are formed in the high-voltage transistor area and the PIP capacitor area, respectively. A gate spacer layer 160 is formed on a lateral side of the gate conductive layer pattern 141. By ion implantation and annealing, an n+ source region 171 and an n+ drain region 272 are formed. Optionally, to form a lightly doped drain structure, ion implantation may be performed prior to forming a gate spacer layer 160 to form source/drain extended regions. Subsequently, a dielectric layer pattern 180 and a second electrode layer pattern 190 are sequentially stacked on the first electrode layer pattern 142 in the PIP capacitor area. By wiring, the n+ source and drain regions 171 and 272 in the high-voltage transistor area are electrically connected to source and drain electrodes S and D, respectively. The first and second electrode layer patterns 142 and 190 in the PIP capacitor area are electrically connected to lower and upper electrodes C1 and C2, respectively. Hence, the high-voltage transistor and the PIP capacitor are formed in the high-voltage transistor area and the PIP capacitor area, respectively.
A current path of the high-voltage transistor, shown by the arrow extending from n+ source region 171, includes a channel region in the substrate 100 under the gate conductive layer pattern 141 and a surface of the n− extended drain region 110. Therefore, resistance is raised along the lightly doped n− extended drain region 110 and an increase in on-resistance of a device occurs. This degrades the electrical characteristics of the device.